Using Cacheline Reuse Characteristics for Prefetcher Throttling

• IRIE Hidetsugu

  University of Electro-Communications

• MIYOSHI Takefumi

  University of Electro-Communications

• HONJO Goki

  The University of Tokyo

• HIRAKI Kei

  The University of Tokyo

• YOSHINAGA Tsutomu

  University of Electro-Communications

抄録

One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E95.D (12), 2928-2938, 2012

  一般社団法人 電子情報通信学会

キーワード

• microarchitecture
• cache
• prefetch

詳細情報

• CRID: 1390282679356181760
• NII論文ID: 120006315524
• NII論文ID: 10031161457
• NII書誌ID: AA10826272
• DOI: 10.1587/transinf.e95.d.2928
• ISSN: 17451361
• ISSN: 09168532
• Web Site: http://id.nii.ac.jp/1438/00000284/
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E95.D/12/E95.D_2928/_pdf
• 本文言語コード: en
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