Using Cacheline Reuse Characteristics for Prefetcher Throttling
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- IRIE Hidetsugu
- University of Electro-Communications
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- MIYOSHI Takefumi
- University of Electro-Communications
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- HONJO Goki
- The University of Tokyo
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- HIRAKI Kei
- The University of Tokyo
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- YOSHINAGA Tsutomu
- University of Electro-Communications
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Abstract
One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.
Journal
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E95.D (12), 2928-2938, 2012
The Institute of Electronics, Information and Communication Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1390282679356181760
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- NII Article ID
- 120006315524
- 10031161457
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- NII Book ID
- AA10826272
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- ISSN
- 17451361
- 09168532
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- Text Lang
- en
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- Data Source
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- JaLC
- IRDB
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed
