ECRプラズマ法によって作製したGe-MIS構造における界面近傍トラップのDLTS評価  [in Japanese] DLTS Evaluation of Near-Interface Traps in Ge-MIS Strustures Fabricated by ECR-Plasma Techniques  [in Japanese]

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Author(s)

Abstract

A Ge-MIS structure has attracted attention for the candidate of a next generation CMOS device. To date, we have successfully developed Ge-MIS structures with superior interface qualities by ECR (Electron Cyclotron Resonance) plasma techniques. In addition, we have shown that DLTS (Deep Level Transient Spectroscopy) method is useful for evaluating the Ge-MIS structures. In this report, we have evaluated the near-interface traps in GeN<sub>x</sub>/Ge structures by DLTS method, and have evaluated the effect of annealing on reducing the traps. The traps observed in the Ge-MIS samples were greatly reduced by 400°C annealing. The origins of the traps are also discussed by comparing with the traps in germanium reported to date.

Journal

  • IEEJ Transactions on Electronics, Information and Systems

    IEEJ Transactions on Electronics, Information and Systems 133(8), 1481-1484, 2013-08-01

    The Institute of Electrical Engineers of Japan

References:  15

Codes

  • NII Article ID (NAID)
    10031189039
  • NII NACSIS-CAT ID (NCID)
    AN10065950
  • Text Lang
    JPN
  • Article Type
    ART
  • ISSN
    03854221
  • NDL Article ID
    024846517
  • NDL Call No.
    Z16-795
  • Data Source
    CJP  NDL  J-STAGE 
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