共有メモリ型並列計算機シミュレータの実現  [in Japanese] A parallel machine simulator with reduction of synchronization event.  [in Japanese]

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Author(s)

    • 今福 茂 IMAFUKU Shigeru
    • 豊橋技術科学大学 工学部 並列処理研究室 Department of Computer Science, Toyohashi University of Technology
    • 大野 和彦 OHNO Kazuhiko
    • 豊橋技術科学大学 工学部 並列処理研究室 Department of Computer Science, Toyohashi University of Technology
    • 中島 浩 NAKASHIMA Hiroshi
    • 豊橋技術科学大学 工学部 並列処理研究室 Department of Computer Science, Toyohashi University of Technology

Abstract

並列計算機の高速化アイディアを特定の実装に因われずに検証する手段としてシミュレーションは有効な手法である。しかし、逐次環境下ではシミュレーション自体に長い時間を要する。その高速化要求を満たす手法として並列シミュレーションがあるが、同期イベントやメッセージ通信を忠実に再現するとシミュレータ上でのメッセージが多発しボトルネックとなる。我々はバリア同期や排他制御などのソフトウェア的な同期イベントのみをシミュレータの同期イベントとして扱う同期イベント削減手法を提案し、並列シミュレータ開発の第一ステップとして、同期イベント削減手法を用いた逐次シミュレータを試作し、最大24%の速度向上を確認した。Simulation of a large computer system such as a parallel machine takes much computation time. Parallelization will be a good solution, but it cause a serious performance bottleneck if we directly map inter-processor hardware events for synchronizations onto those of parallel simulation. Our idea for efficient parallelization is to map software level synchronization events, such as barriers and mutexes, to simulator's events to avoid the bottleneck. This idea is also applicable to a sequential simulator because it reduce the frequency of the context switch. In this research, we implemented a sequential simulator with the event reduction method. We evaluated its performance and compare it with a direct event mapping. As the result, the event reduction achieves about 24% speed up proving its efficiency.

Simulation of a large computer system such as a parallel machine takes much computation time. Parallelization will be a good solution, but it cause a serious performance bottleneck if we directly map inter-processor hardware events for synchronizations onto those of parallel simulation. Our idea for efficient parallelization is to map software level synchronization events, such as barriers and mutexes, to simulator's events to avoid the bottleneck. This idea is also applicable to a sequential simulator because it reduce the frequency of the context switch. In this research, we implemented a sequential simulator with the event reduction method. We evaluated its performance and compare it with a direct event mapping. As the result, the event reduction achieves about 24% speed up proving its efficiency.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 1999(67(1999-ARC-134)), 37-42, 1999-08-02

    Information Processing Society of Japan (IPSJ)

References:  8

Cited by:  1

Codes

  • NII Article ID (NAID)
    110002774784
  • NII NACSIS-CAT ID (NCID)
    AN10096105
  • Text Lang
    JPN
  • Article Type
    Journal Article
  • ISSN
    09196072
  • NDL Article ID
    5338427
  • NDL Call No.
    Z14-1121
  • Data Source
    CJP  CJPref  NDL  NII-ELS  IPSJ 
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