Proposal for Next Generation High Speed Serial Link Architecture

• HIRONAKA Tetsuo

  Department of Computer Engineering, Faculty of Information Science, Hiroshima City University

• TSUCHIE Tatsuo

  Department of Computer Engineering, Faculty of Information Science, Hiroshima City University

Bibliographic Information

Other Title

• 次世代の高速大容量シリアルリンクアーキテクチャの提案

Abstract

As the I/O bus speed of LSI grows faster, the more the bus line delay cause trouble. For high speed bus we can not except all signals to reach the receivers within the same clock, that means bus line skew would cause trouble. In this paper we propose a new skew proof bus architecture with the ability to achieve scalable high band width by increasing the number of bus lines.

Journal

• IPSJ SIG Notes

  IPSJ SIG Notes 126 31-36, 1997-10-28

  Information Processing Society of Japan (IPSJ)

Details

• CRID: 1573950401830709120
• NII Article ID: 110002775149
• NII Book ID: AN10096105
• ISSN: 09196072
• Text Lang: ja
• Data Source:
  • CiNii Articles