Partial Order Reduction に基づく Timed 回路の safety/timing failure 検出アルゴリズムの効率化について Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

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Author(s)

Abstract

実時間の概念を含まない従来のトレース理論に基づく非同期式回路検証方式を拡張し,有限幅遅延を持つ非同期式回路(timed回路)を扱えるように拡張した検証方式が既に提案されている.本稿では,その検証方式を高速化するために,検証に必要な状態空間のみを探索するoartial order reduction技術を適用する方法について述べる.

This paper proposes a timed trace theoretic verification algorithm with partial order reduction technique so that both the safety failures and timing failures of timed circuits can be efficiently detected. This algorithm follows the framework of the timed trace theoretic verification that is constructed in accordance with the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits.

Journal

  • IEICE technical report. Dependable computing

    IEICE technical report. Dependable computing 102(658), 25-30, 2003-02-14

    The Institute of Electronics, Information and Communication Engineers

References:  5

Codes

  • NII Article ID (NAID)
    110003173584
  • NII NACSIS-CAT ID (NCID)
    AA11645397
  • Text Lang
    ENG
  • Article Type
    ART
  • ISSN
    09135685
  • NDL Article ID
    6506780
  • NDL Source Classification
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL Call No.
    Z16-940
  • Data Source
    CJP  NDL  NII-ELS 
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