A Prototype Router VLSI for Massively Parallel Computer RWC-1

• YOKOTA Takashi

  Tsukuba Research Center, Real World Computing Partnership

• MATSUOKA Hiroshi

  Tsukuba Research Center, Real World Computing Partnership

• OKAMOTO Kazuaki

  Tsukuba Research Center, Real World Computing Partnership

• HIRONO Hideo

  Tsukuba Research Center, Real World Computing Partnership

• HORI Atsushi

  Tsukuba Research Center, Real World Computing Partnership

• SAKAI Shuichi

  Tsukuba Research Center, Real World Computing Partnership

Bibliographic Information

Other Title

• RWC-1相互結合網用プロトタイプ・ルータの設計

Abstract

We have proposed a low-degree and high-performance interconnection network MDCE (Multidimensional Directed Cycles Ensemble extension) for the massively parallel computer RWC-1. This paper describes the first router VLSI chip realizing three dimensional MDCE networks. We first discuss required functions for effective system management such as partitioning and time-sharing, and many of them are implemented in the router. We then explain the outline of the prototype chip design. A router is realized by cooperating 3 identical chips. The chip has about 174,000 gates and has been designed and fabricated in a 0.6μm CMOS gate array.

Journal

• IEICE technical report. Computer systems

  IEICE technical report. Computer systems 95 (125), 49-54, 1995-06-23

  The Institute of Electronics, Information and Communication Engineers

Details

• CRID: 1571698602338560896
• NII Article ID: 110003180085
• NII Book ID: AN10013141
• Text Lang: ja
• Data Source:
  • CiNii Articles