Design and Efficient Implementation of a Modulated Complex Lapped Transform Processor Using Pipelining Technique

• TAI Heng-Ming

  The Department of Electrical Engineering, University of Tulsa

• JING Changyou

  Snap-On Diagnostics

抄録

This paper presents the design of a modulated complex lapped transform (MCLT) processor and its complex programmable logic device (CPLD) implementation. The MCLT is a 2x oversampled DFT filter bank; it performs well in applications that require a complex filter bank, such as noise reduction and acoustic echo cancellation. First, we show that the MCLT can be mapped to a Fast Fourier Transform (FFT). Then efficient implementation for fast MCLT computation is realized on the CPLD hardware using pipelining techniques. Detailed circuit design for the MLCT processor is presented, as well as timing diagrams for design verification and performance evaluation.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 84 (5), 1280-1287, 2001-05-01

  一般社団法人電子情報通信学会

キーワード

• modulated lapped transform
• FFT
• DCT
• pipelining
• programmable logic device

詳細情報

• CRID: 1571417127333796096
• NII論文ID: 110003208933
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
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