Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface

• Tan, Boon-Keat

• Yoshimura, Ryuji

• Matsuoka, Toshimasa

• Taniguchi, Kenji

抄録

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm × 4.5 mm chip using 0.6 µm CMOS process.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E84-D (11), 1521-1527, 2001-11

  電子情報通信学会

キーワード

• CDMA bus
• parallel processing
• interconnection topology
• routing flexibility
• fault tolerant

詳細情報

• CRID: 1050018218950027392
• NII論文ID: 110003210431
• NII書誌ID: AA10826272
• HANDLE: 11094/51672
• ISSN: 09168532
• 本文言語コード: en
• 資料種別: journal article
• データソース種別:
  • IRDB
  • CiNii Articles