Si Substrate Resistivity Design for On-Chip Matching Circuit Based on Electro-Magnetic Simulation

• ONO Masayoshi

  nformation Technology R&D Center, Mitsubishi Electric Corpration

• SUEMATSU Noriharu

  nformation Technology R&D Center, Mitsubishi Electric Corpration

• KUBO Shunji

  System LSI Division, Mitsubishi Electric Corpration

• NAKAJIMA Kensuke

  nformation Technology R&D Center, Mitsubishi Electric Corpration

• IYAMA Yoshitada

  nformation Technology R&D Center, Mitsubishi Electric Corpration

• TAKAGI Tadashi

  nformation Technology R&D Center, Mitsubishi Electric Corpration

• ISHIDA Osami

  nformation Technology R&D Center, Mitsubishi Electric Corpration

抄録

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electromagnetic simulation, the relationship between coplanar wave-guide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 84 (7), 923-930, 2001-07-01

  一般社団法人電子情報通信学会

キーワード

• Si-MMIC
• electro-magnetic simulation
• high resistivity Si substrate
• low noise amplifier
• spiral inductor

詳細情報

• CRID: 1570572702512343936
• NII論文ID: 110003212256
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: fr
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