Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA

• MATSUMOTO Yuya

  Department of Electrical and Electronics Engineering, Sophia University

• TANJI Yuichi

  Department of Reliability-based Information Systems Engineering, Kagawa University

• TANAKA Mamoru

  Department of Electrical and Electronics Engineering, Sophia University

抄録

This paper describes a sparse realization of passive reduced-order interconnect models via PRIMA to provide the SPICE compatible models. It is demonstrated that, if the SPICE models are directly realized so that the reduced-order equations obtained via PRIMA are stamped into the MNA matrix, the simulations of networks containing the macromodels become computationally inefficient when size of the reduced-order equations is relatively large. This is due to dense coefficient matrices of the reduced-order equations resulting from congruent transformations in PRIMA. To overcome this disadvantage, we propose a sparse realization of the reduced-order models. Since the expression is equivalent to the reduced-order equations, the passivity of the SPICE models generated is also guaranteed. Computational efficiency on SPICE is demonstrated in performing the transient analysis of circuits containing the proposed macromodels.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 87 (1), 251-257, 2004-01-01

  一般社団法人電子情報通信学会

キーワード

• signal integrity
• interconnects
• passive reduced-order models
• PRIMA
• SPICE

詳細情報

• CRID: 1572543027348198400
• NII論文ID: 110003212757
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
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