-
- KAWAZU Hideki
- Department of Computer Science, Waseda University
-
- UCHIDA Jumpei
- Department of Computer Science, Waseda University
-
- MIYAOKA Yuichiro
- Department of Computer Science, Waseda University
-
- TOGAWA Nozomu
- Department of Computer Science, Waseda University
-
- YANAGISAWA Masao
- Department of Computer Science, Waseda University
-
- OHTSUKI Tatsuo
- Department of Computer Science, Waseda University
この論文をさがす
抄録
A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b=k×n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.
収録刊行物
-
- IEICE transactions on fundamentals of electronics, communications and computer sciences
-
IEICE transactions on fundamentals of electronics, communications and computer sciences 88 (4), 876-884, 2005-04-01
一般社団法人電子情報通信学会
- Tweet
キーワード
詳細情報 詳細情報について
-
- CRID
- 1571980077395773824
-
- NII論文ID
- 110003213389
-
- NII書誌ID
- AA10826239
-
- ISSN
- 09168508
-
- 本文言語コード
- en
-
- データソース種別
-
- CiNii Articles