Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access

• HARIYAMA Masanori

  Graduate School of Information Sciences, Tohoku University

• SASAKI Haruka

  Graduate School of Information Sciences, Tohoku University

• KAMEYAMA Michitaka

  Graduate School of Information Sciences, Tohoku University

Abstract

This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.

Journal

• IEICE Trans. Info. and Syst., D

  IEICE Trans. Info. and Syst., D 88 (7), 1486-1491, 2005-07-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• stereo vision
• SAD (sum of absolute differences)
• memory allocation
• logic-in-memory architecture

Details

• CRID: 1572824502324565120
• NII Article ID: 110003214339
• NII Book ID: AA10826272
• ISSN: 09168532
• Text Lang: en
• Data Source:
  • CiNii Articles