Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation

• NAMBA Kazuteru

  Faculty of Engineering, Chiba University

• ITO Hideo

  Faculty of Engineering, Chiba University

抄録

In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.

収録刊行物

• IEICE transactions on information and systems

  IEICE transactions on information and systems 88 (9), 2135-2142, 2005-09-01

  一般社団法人電子情報通信学会

キーワード

• two-pattern testing
• adjacency test
• deterministic test generation
• BIST

詳細情報

• CRID: 1570572702512033280
• NII論文ID: 110003214421
• NII書誌ID: AA10826272
• ISSN: 09168532
• 本文言語コード: en
• データソース種別:
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