A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic

• DEGAWA Katsuhiko

  Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University

• AOKI Takafumi

  Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University

• HIGUCHI Tatsuo

  Department of Electronics, Faculty of Engineering, Tohoku Institute of Technology

• INOKAWA Hiroshi

  NTT Basic Research Laboratories, NTT Corporation

• TAKAHASHI Yasuo

  Graduate School of Information Science and Technology, Hokkaido University

Abstract

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

Journal

• IEICE Trans. Electron., C

  IEICE Trans. Electron., C 87 (11), 1827-1836, 2004-11-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• single-electron transistors
• multiple-valued logic
• quantum devices
• logic circuits
• parallel counters

Details

• CRID: 1570291227534265216
• NII Article ID: 110003214798
• NII Book ID: AA10826283
• ISSN: 09168524
• Text Lang: en
• Data Source:
  • CiNii Articles