Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories

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Author(s)

Abstract

This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.

Journal

  • IEICE transactions on electronics

    IEICE transactions on electronics 88(2), 255-263, 2005-02-01

    The Institute of Electronics, Information and Communication Engineers

References:  7

Codes

  • NII Article ID (NAID)
    110003215116
  • NII NACSIS-CAT ID (NCID)
    AA10826283
  • Text Lang
    ENG
  • Article Type
    ART
  • ISSN
    09168524
  • Data Source
    CJP  NII-ELS 
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