Evaluation of Shared DRAM for Parallel Processor System with Shared Memory

  • KURINO Hiroyuki
    the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University
  • HIRANO Keiichi
    the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University
  • ONO Taizo
    the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University
  • KOYANAGI Mitsumasa
    the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University

この論文をさがす

抄録

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1.5μm CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.

収録刊行物

被引用文献 (2)*注記

もっと見る

参考文献 (4)*注記

もっと見る

詳細情報

  • CRID
    1570854177488061440
  • NII論文ID
    110003216451
  • NII書誌ID
    AA10826239
  • ISSN
    09168508
  • 本文言語コード
    en
  • データソース種別
    • CiNii Articles

問題の指摘

ページトップへ