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- KURINO Hiroyuki
- the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University
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- HIRANO Keiichi
- the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University
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- ONO Taizo
- the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University
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- KOYANAGI Mitsumasa
- the Dept. of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University
この論文をさがす
抄録
We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1.5μm CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.
収録刊行物
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- IEICE transactions on fundamentals of electronics, communications and computer sciences
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IEICE transactions on fundamentals of electronics, communications and computer sciences 81 (12), 2655-2660, 1998-12-01
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詳細情報
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- CRID
- 1570854177488061440
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- NII論文ID
- 110003216451
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- NII書誌ID
- AA10826239
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- ISSN
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles