A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect

• IBARAGI Eitake

  Department of Electrical and Engineering Science University of Tokyo

• HYOGO Akira

  Department of Electrical and Engineering Science University of Tokyo

• SEKINE Keitaro

  Department of Electrical and Engineering Science University of Tokyo

抄録

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. Their gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V_<p-p> input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 82 (2), 327-334, 1999-02-25

  一般社団法人電子情報通信学会

キーワード

• analog signal processing
• MOS analog circuit
• analog multiplier
• mobility reduction
• body effect

詳細情報

• CRID: 1572261552372329472
• NII論文ID: 110003216549
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
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