Scheduling Algorithm with Consideration to Void Space Reduction in Photonic Packen Switch

• YAMAGUCHI Takashi

  Graduate School of Engineering Science, Osaka University

• BABA Ken-ichi

  Cybermedia Center, Osaka University

• MURATA Masayuki

  Cybermedia Center, Osaka University

• KITAYAMA Ken-ichi

  Graduate School of Engineering, Osaka University

抄録

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an out-put buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced by its architecture and a packet scheduling algorithm. We compare the performances of these two packet switches by applying different packet scheduling algorithms. Through simulation experiments, we show that each architecture has a parameter region for achieving better performance. For the shared buffer type switch, we found that void space introduces unacceptable performance degradation when the traffic load is high. Accordingly, we propose a void space reduction method. Our simulation results show that our proposed method enables to the shared buffer type switch to outperform the output buffer type switch even under high traffic load conditions.

収録刊行物

• IEICE transactions on communications

  IEICE transactions on communications 86 (8), 2310-2318, 2003-08-01

  一般社団法人電子情報通信学会

キーワード

• WDM
• photonic packet switch
• FDL buffer
• variable lenght size packet
• packet scheduling algorithm

詳細情報

• CRID: 1572543027200505344
• NII論文ID: 110003221974
• NII書誌ID: AA10826261
• ISSN: 09168516
• 本文言語コード: en
• データソース種別:
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