Signal Transmission and Coding Architecture for Next-Generation Ethernet

• TOYODA Hidehiro

  Central Research Laboratory, Hitachi, Ltd.

• NISHI Hiroaki

  Faculty of Science and Technology, Keio University

• NISHIMURA Shinji

  Central Research Laboratory, Hitachi, Ltd.

• KANAI Hisaaki

  Production Engineering Research Laboratory, Hitachi, Ltd.

• HARASAWA Katsuyoshi

  Hitachi Hybrid Network Co., Ltd.

抄録

The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s × 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.

収録刊行物

• IEICE transactions on information and systems

  IEICE transactions on information and systems 86 (11), 2317-2324, 2003-11-01

  一般社団法人電子情報通信学会

キーワード

• 100-Gigabit Ethernet
• 64B
• 66B
• skew compensation

詳細情報

• CRID: 1571135652318346752
• NII論文ID: 110003223178
• NII書誌ID: AA10826272
• ISSN: 09168532
• 本文言語コード: en
• データソース種別:
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