A 500MHz 4Mb CMOS Pipeline-Burst Cache SRAM

• TAKEDA Koichi

  Silicon Systems Research Labs., NEC Corporation

• NAKAMURA Kazuyuki

  Silicon Systems Research Labs., NEC Corporation

• TOYOSHIMA Hideo

  Silicon Systems Research Labs., NEC Corporation

• NODA Kenji

  ULSI Device Development Labs., NEC Corporation

• OHKUBO Hiroaki

  ULSI Device Development Labs., NEC Corporation

• UCHIDA Tetsuya

  ULSI Device Development Labs., NEC Corporation

• SHIMIZU Toshiyuki

  Second LSI Memory Div., NEC Corporation

• ITANI Toshiro

  ULSI Device Development Labs., NEC Corporation

• TOKASHIKI Ken

  ULSI Device Development Labs., NEC Corporation

• KISHIMOTO Koji

  ULSI Device Development Labs., NEC Corporation

Bibliographic Information

Other Title

• 500MHz動作4Mb CMOSキャッシュSRAM

Abstract

A secondary cache SRAM is an indispensable CPU partner in a high-performance system. The main objectives are 1) pipeline-burst operation, 2) 32b 500MHz (2GB/s) I/Os, and 3) point-to-point communication with a CPU, as well as shortened latency and reduced noise and power caused by high-speed, high-bandwidth I/O operation.

Journal

• Technical report of IEICE. DSP

  Technical report of IEICE. DSP 97 (314), 39-46, 1997-10-16

  The Institute of Electronics, Information and Communication Engineers

Keywords

• Cache
• SRAM
• High-speed
• Interface
• Bandwidth

Details

• CRID: 1570572702485465728
• NII Article ID: 110003279499
• NII Book ID: AN10060786
• ISSN: 09135685
• Text Lang: ja
• Data Source:
  • CiNii Articles