DIBLを用いた低消費電力回路形式のための最適デバイス設計  [in Japanese] Optimum Device Consideration for Standby Power Reduction Scheme Using Drain Induced Barrier Lowering (DIBL)  [in Japanese]

Search this Article

Author(s)

Abstract

Drain Induced Barrier Lowering (DIBL)を利用してスタンバイパワーを減少させる回路形式について,最適なデバイス構成,特に最適なDIBLの値をシミュレーションにより検討した.この回路形式では,DIBL効果を緩和するためにスタンバイ時において電源電圧を下げる.これにより,閾値電圧が増大してリーク電流を減少させることができる.最適のDIBLの値は,臨界電圧Voと電源電圧の大小によって異なることが明らかとなった.即ち,スタンバイ時における電源電圧をVoより下げられる場合は,より大きなDIBL値を持つデバイスの方がスタンバイパワーを抑制することができる.また,この回路形式を用いることにより,しきい値電圧ばらつきによるスタンバイリーク電流のばらつきが抑制されることも明らかとなった.

The optimum device for a standby power reduction scheme utilizing drain-induced barrier lowering (DIBL) has been investigated. In this scheme, supply voltage is lowered in the standby mode to relax DIBL effect, resulting in the increase in threshold voltage and the reduction of subthreshold leakage current. It is found that a critical supply voltage, Vo, exists that determines the optimum DIBL value for the standby power suppression. It is also shown that the fluctuations of standby power due to the threshold voltage variation can be suppressed in this circuit scheme utilizing DIBL.

Journal

  • Technical report of IEICE. SDM

    Technical report of IEICE. SDM 102(489), 17-22, 2002-11-22

    The Institute of Electronics, Information and Communication Engineers

References:  17

  • <no title>

    HIRAMOTO T.

    Jpn. J. Appl. Phys. 40, 2854, 2001

    Cited by (1)

  • <no title>

    INUKAI T.

    Technical Digest of Custom Integrated Circuits Conference (CICC), 2000, 2000

    Cited by (1)

  • <no title>

    NOSE K.

    PhD Thesis, University of Tokyo, 2002

    Cited by (1)

  • <no title>

    YE Y.

    Technical Digest of Symposium on VLSI Circuits, 1998, 1998

    Cited by (1)

  • <no title>

    ENOMOTO T.

    Proceedings of the European Solid-Sates Circuits Conference, 2002, 2002

    Cited by (1)

  • <no title>

    HU H.

    IEEE Trans. Electron Devices 42, 669, 1995

    Cited by (1)

  • <no title>

    Avant! Corp.

    Medici, 1998

    Cited by (1)

  • <no title>

    LIU Q.

    International Conference on Solid State Devices and Materials (SSDM), 2002, 2002

    Cited by (1)

  • <no title>

    NARENDA S.

    International Symposium on Low Power Electronics and Devices (ISLPED), 1999, 1999

    Cited by (1)

  • <no title>

    THOMPSON S.

    Technical Digest of International Electron Devices Meeting (IEDM), 2001, 2001

    Cited by (1)

  • <no title>

    International Technology Roadmap for Semiconductors, 2001

    Cited by (1)

  • <no title>

    INUKAI T.

    Jpn. J. Appl. Phys. 41, 2312, 2002

    Cited by (1)

  • <no title>

    KOURA H.

    Jpn. J. Appl. Phys. 39, 2312, 2000

    Cited by (1)

  • <no title>

    SUN S. W.

    IEEE J. Solid-State Circuits 30, 947, 1995

    Cited by (1)

  • <no title>

    KURODA T.

    IEEE J. SSC 31, 1770, 1996

    DOI  Cited by (128)

  • <no title>

    MUHTOH S.

    IEEE J. Solid-State Circuits 30(8), 847-854, 1995

    DOI  Cited by (146)

  • Device scaling limits of Si MOSFETs and their application dependencies

    FRANK D. J.

    Proc. IEEE 89(3), 259-288, 2001

    DOI  Cited by (15)

Codes

  • NII Article ID (NAID)
    110003308095
  • NII NACSIS-CAT ID (NCID)
    AN10013254
  • Text Lang
    JPN
  • Article Type
    ART
  • ISSN
    09135685
  • NDL Article ID
    6400688
  • NDL Source Classification
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL Call No.
    Z16-940
  • Data Source
    CJP  NDL  NII-ELS 
Page Top