Technology for module design with the source synchronous bus for the high energy heavy ion physics

Bibliographic Information

Other Title
  • 高エネルギー物理実験のためのソースシンクロナスバスを用いたモジュール化技術

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Abstract

The ordinary synchronous bus architecture with a common timing clock has linitation in the number of modules or data transfer speed because of clock skew and interconnect delay. In order to cope with this difficulty, we have been developing a data readout system with the source synchronous bus architecture, where the timing reference is locally generated in a data-sending module, and is provided to a data-receiving module. In this paper, we describe the front end readout system(front end electronics)with the source synchronous bus on a 9U custom back-plane, which is used for an experiment in high energy heavy ion physics.

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 98 (459), 1-6, 1998-12-11

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1573668927228292096
  • NII Article ID
    110003317030
  • NII Book ID
    AN10013276
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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