Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation

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Author(s)

    • KITAI Tomoya
    • Graduate School of Information Science and Engineering, Department of Computer Science, Tokyo Institute of Technology
    • YONEDA Tomohiro
    • Infrastructure Systems Research Division, National Institute of Informatics
    • MYERS Chris
    • Department of Electrical and Computer Engineering, University of Utah

Abstract

This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure are obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.

Journal

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 88(11), 2555-2564, 2005-11-01

    The Institute of Electronics, Information and Communication Engineers

References:  12

Codes

  • NII Article ID (NAID)
    110003502000
  • NII NACSIS-CAT ID (NCID)
    AA10826272
  • Text Lang
    ENG
  • Article Type
    ART
  • ISSN
    09168532
  • Data Source
    CJP  NII-ELS 
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