Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications

• KOMATSU Satoshi

  VLSI Design and Education Center, The University of Tokyo

• FUJITA Masahiro

  VLSI Design and Education Center, The University of Tokyo

抄録

Energy consumption is one of the most critical constraints in the current VLSI system designs. In addition, fault tolerance of VLSI systems will be also one of the most important requirements in the future shrunk VLSIs. This paper proposes practical low power and fault tolerant bus encoding methods in on-chip data transfer. The proposed encoding methods use the combination of simple low power code and fault tolerant code. Experimental results show that the proposed methods can reduce signal transitions by 23% on the bus with fault tolerance. In addition, circuit implementation results with bus signal swing optimization show the effectiveness of the proposed encoding methods. We show also the selection methodology of the optimum encoding method under the given requirements.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 88 (12), 3282-3289, 2005-12-01

  一般社団法人電子情報通信学会

キーワード

• bus encoding
• ECC
• EDC
• low power
• reliability

詳細情報

• CRID: 1572824501859403136
• NII論文ID: 110004019428
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
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