Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip.

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  • Lee Kang Wook
    Department of Machine Intelligence and Systems Engineering,Tohoku University,<BR> 01 Aza-Aoba Aramaki, Aoba-ku, Sendai 980-8579, Japan
  • Nakamura Tomonori
    Department of Machine Intelligence and Systems Engineering,Tohoku University,<BR> 01 Aza-Aoba Aramaki, Aoba-ku, Sendai 980-8579, Japan
  • Sakuma Katsuyuki
    Department of Machine Intelligence and Systems Engineering,Tohoku University,<BR> 01 Aza-Aoba Aramaki, Aoba-ku, Sendai 980-8579, Japan
  • Park Ki Tae
    Department of Machine Intelligence and Systems Engineering,Tohoku University,<BR> 01 Aza-Aoba Aramaki, Aoba-ku, Sendai 980-8579, Japan
  • Shimazutsu Hiroaki
    Research Center, Mitsubishi Heavy Co., Hiroshima 733-8553, Japan
  • Miyakawa Nobuaki
    Advanced Technology Center, Fuji Xerox Co., Kanagawa 243-04, Japan
  • Kim Ki Yoon
    Japan Science and Technology Corporation(CREST), Tokyo 101-0032, Japan
  • Kurino Hiroyuki
    Department of Machine Intelligence and Systems Engineering,Tohoku University,<BR> 01 Aza-Aoba Aramaki, Aoba-ku, Sendai 980-8579, Japan
  • Koyanagi Mitsumasa
    Department of Machine Intelligence and Systems Engineering,Tohoku University,<BR> 01 Aza-Aoba Aramaki, Aoba-ku, Sendai 980-8579, Japan

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A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

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