100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet

• TOYODA Hidehiro

  Central Research Laboratory, Hitachi, Ltd.

• NISHIMURA Shinji

  Central Research Laboratory, Hitachi, Ltd.

• OKUNO Michitaka

  Central Research Laboratory, Hitachi, Ltd.

• FUKUDA Kouji

  Central Research Laboratory, Hitachi, Ltd.

• NAKAHARA Kouji

  Central Research Laboratory, Hitachi, Ltd.

• NISHI Hiroaki

  Faculty of Science and Technology, Keio University

Abstract

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12×10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits×10 lanes). One conveys forward error correction code ((132b, 140b) Hamming code), providing highly reliable (BER<10^<-12>) data transmission, and the other conveys parity data, enabling faultlane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the laneto-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590k gate circuit, which is small enough for implementation in a single LSI circuit.

Journal

• IEICE Transaction on Communication, B

  IEICE Transaction on Communication, B 89 (3), 696-703, 2006-03-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• Ethernet
• MAN
• skew
• FEC

Details

• CRID: 1572824501797899648
• NII Article ID: 110004656605
• NII Book ID: AA10826261
• ISSN: 09168516
• Text Lang: en
• Data Source:
  • CiNii Articles