Average Power Reduction in Scan Testing by Test Vector Modification

• KAJIHARA Seiji

  Graduate School of Computer Science and Systems Engineering, Kyushu Institute of technology

• ISHIDA Koji

  Graduate School of Computer Science and Systems Engineering, Kyushu Institute of technology

• MIYASE Kohei

  Graduate School of Computer Science and Systems Engineering, Kyushu Institute of technology

抄録

This paper presents a test vector modification method for reducing average power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 45% of the original test sets in average.

収録刊行物

• IEICE transactions on information and systems

  IEICE transactions on information and systems 85 (10), 1483-1489, 2002-10-01

  一般社団法人電子情報通信学会

キーワード

• test power reduction
• scan testing
• ATPG
• test modification

詳細情報

• CRID: 1570291227307159296
• NII論文ID: 110006376577
• NII書誌ID: AA10826272
• ISSN: 09168532
• 本文言語コード: en
• データソース種別:
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