IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates

• HASHIZUME Masaki

  Faculty of Engineering, The University of Tokushima

• TAKEDA Teppei

  Faculty of Engineering, The University of Tokushima

• ICHIMIYA Masahiro

  Faculty of Engineering, The University of Tokushima

• YOTSUYANAGI Hiroyuki

  Faculty of Engineering, The University of Tokushima

• MIURA Yukiya

  Graduate School of Engineering, Tokyo Metropolitan University

• KINOSHITA Kozo

  Faculty of Informatics, Osaka Gakuin University

Abstract

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_<DDQ> sensor design and external I_<DDQ> sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.

Journal

• IEICE transactions on information and systems

  IEICE transactions on information and systems 85 (10), 1534-1541, 2002-10-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• IDDQ sensor
• CMOS
• IDDQ test
• bridging fault

Details

• CRID: 1570854177260582912
• NII Article ID: 110006376583
• NII Book ID: AA10826272
• ISSN: 09168532
• Text Lang: en
• Data Source:
  • CiNii Articles