VSP(Variable Stages Pipeline)の低消費電力、高性能化  [in Japanese] Improvent of VSP (Variable Stages Pipeline) for Low Energy and High Performance Computing  [in Japanese]

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Abstract

近年,モバイルコンピューティングからハイパフォーマンスコンピューティングに至るまで,幅広い分野において低消費エネルギーと高性能の両立が要求されており,様々な手法が研究されている.現在行われている低消費エネルギー化の手法の一つとしてDVSがある.しかし,この手法は将来的に消費エネルギー削減効率の低下が予想される.なぜなら近年CMOSの電源電圧は低下の一途をたどり,電源電圧の下げ幅は小さくなっているからである.そこで我々は,電源電圧に依存しない低消費エネルギー手法として可変パイプライン段数アーキテクチャ(VSP)を提案している.VSPとはパイプライン段数を動的に変化させ,同時にグリッチの緩和を行うことで,高性能と低消費エネルギーの両立を目指す手法である.VSPは高性能と低消費電力の両立を実現できるが,VSPの要素技術であるLDS-Cellを導入することでパイプラインレジスタの遅延増大を招くという問題があった.LDS-cellとはパイプラインステージ間に存在するD-FFの動作を動的にD-ラッチへ変化させることでパイプライン統合と同時にグリッチの緩和を行うものである.そこで本論文ではVSP手法を実現する上で重要なセルであるLDS-cellの改良及び評価を行った.提案手法を詳細設計し,評価したところ,従来のLDS-cell と比較して15%程度高速化できた.Recently, in the field of not only mobile computing but also high performance computing, the achivement of low energy computing and high performance computing is required simul taneously. The DVS (Dynamic Voltage Scaling) is one of the current major methodoligics for low power devices. However by DVS, the lower the chip voltage becomes in the future, the less energy saving we get by DVS. So, in order to reduce the power consumption for lower voltage devices, we propose VSP (Variable Stages Pipeline) processor with the LDS-cell that unifies pipeline stages dynamically and also decreases power consumption caused by glitch propagations on low energy mode. But, because the delay of the LDS-cell is larger than a D-FF, the maximum clock rate for VSP must be lower than the original processor. So this paper improves the LDS-cell to reduce latency and power consumption. According to evaluation results, the improved LDS-cell can achieve 15% faster than the conventional LDS-cell.

Recently, in the field of not only mobile computing but also high performance computing, the achivement of low energy computing and high performance computing is required simultaneously.The DVS (Dynamic Voltage Scaling) is one of the current major methodoligics for low power devices. However by DVS, the lower the chip voltage becomes in the future, the less energy saving we get by DVS. So, in order to reduce the power consumption for lower voltage devices, we propose VSP (Variable Stages Pipeline) processor with the LDS-cell that unifies pipeline stages dynamically and also decreases power consumption caused by glitch propagations on low energy mode. But, because the delay of the LDS-cell is larger than a DFF, the maximum clock rate for VSP must be lower than the original processor. So this paper improves the LDS-cell to reduce latency and power consumption. According to evaluation results, the improved LDS-cell can achieve 15% faster than the conventional LDS-cell.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 2007(79(2007-ARC-174)), 109-114, 2007-08-02

    Information Processing Society of Japan (IPSJ)

References:  8

Cited by:  1

Codes

  • NII Article ID (NAID)
    110006420493
  • NII NACSIS-CAT ID (NCID)
    AN10096105
  • Text Lang
    JPN
  • Article Type
    Journal Article
  • ISSN
    09196072
  • NDL Article ID
    8897797
  • NDL Source Classification
    ZM13(科学技術--科学技術一般--データ処理・計算機)
  • NDL Call No.
    Z14-1121
  • Data Source
    CJP  CJPref  NDL  NII-ELS  IPSJ 
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