可変レベルキャッシュの書き戻しペナルティ軽減手法の提案  [in Japanese] Reduce penalty of flushing of Variable Level Cache  [in Japanese]

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Abstract

現在,プロセッサには高性能と低消費エネルギーの両立が求められている.特に,回路の微細化にともないキャッシュメモリ内でのリークエネルギーが年々増加しているため,これを削減する事が重要である.そこで我々は,可変レベルキャッシュを提案している.可変レベルキャッシュは,動的にキャッシュの要求性能を判断し,あまり性能が必要ないと判断したときにキャッシュの半分をスリープモードに移行し1つ下位のレベルの Exclusive cache として動作する事で,消費電力の削減と性能の維持を両立させる手法である.しかし,可変レベルキャッシュは省電力モードから通常モード時に遷移した際にキャッシュ内のデータを下位の記憶層に書き戻しを行っているが,そのオーバヘッドが問題となっていた.本稿では,このオーバヘッドを軽減するように可変レベルキャッシュを改良し,シミュレーションによる評価を行った.Power dissipation is one major concern not only for mobile computing but also high performance computing, and achieving both low energy and high performance at the same time is required. Especially, it is important to reduce leakage energy consumed in a cache memory because power dissipation by leakage current is dominant factor in deep submicron technologies and a cache memory consists of a large number of transistors. In order to reduce the problem, Variable Level Cache is proposed to achieve both low energy consumption and high performance simultaneously. Variable Level Cache analyzes cache performance and if it detects that the running program does not need so large capacity of cache memory, half of the cache memory is put into standby mode, and is treated as a lower level exclusive cache. But conventional Variable Level Cache needs to flush date in cache memory when it is changed from low-energy mode to normal mode, and the overhead lowers performance. This paper improves Variable Level Cache to reduce the overhead of mode changing, and shows effectiveness of our approach by simulation.

Power dissipation is one major concern not only for mobile computing but also high performance computing, and achieving both low energy and high performance at the same time is required. Especially, it is important to reduce leakage energy consumed in a cache memory because power dissipation by leakage current is dominant factor in deep submicron technologies and a cache memory consists of a large number of transistors. In order to reduce the problem, Variable Level Cache is proposed to achieve both low energy consumption and high performance simultaneously. Variable Level Cache analyzes cache performance and if it detects that the running program does not need so large capacity of cache memory, half of the cache memory is put into standby mode, and is treated as a lower level exclusive cache. But conventional Variable Level Cache needs to flush date in cache memory when it is changed from low-energy mode to normal mode, and the overhead lowers performance. This paper improves Variable Level Cache to reduce the overhead of mode changing, and shows effectiveness of our approach by simulation.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 2007(115(2007-ARC-175)), 51-56, 2007-11-22

    Information Processing Society of Japan (IPSJ)

References:  12

Cited by:  1

Codes

  • NII Article ID (NAID)
    110006533749
  • NII NACSIS-CAT ID (NCID)
    AN10096105
  • Text Lang
    JPN
  • Article Type
    Journal Article
  • ISSN
    09196072
  • NDL Article ID
    9290909
  • NDL Source Classification
    ZM13(科学技術--科学技術一般--データ処理・計算機)
  • NDL Call No.
    Z14-1121
  • Data Source
    CJP  CJPref  NDL  NII-ELS  IPSJ 
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