A Field-programmable VLSI based on an asynchronous bit-serial architecture

• Hariyama, Masanori

• Ishihara, Shota

• Chang, Chia Wei

• Kameyama, Michitaka

Abstract

application/pdf

学術論文 (Article)

科研費報告書収録論文(課題番号:17300009/研究代表者:亀山充隆/システムインテグレーション理論に基づく高安全知能自動車用VLSIの最適設計)

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Journal

• IEEE Asian Solid-State Circuits Conference, 2007. ASSCC '07

  IEEE Asian Solid-State Circuits Conference, 2007. ASSCC '07 107 (382), 380-383, 2007

  Institute of Electrical and Electronics Engineers

Keywords

• FPGA
• 非同期アーキテクチャ
• LEDR符号化
• 2線符号化
• Asynchronous architecture
• LEDR encoding
• Dual-rail encoding

Details

• CRID: 1050001202728927360
• NII Article ID: 110006546969
• NII Book ID: AA1123312X
• ISSN: 09135685
• HANDLE: 10097/40012
• NDL BIB ID: 9327971
• Web Site: https://tohoku.repo.nii.ac.jp/records/66827
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I9327971
• Text Lang: en
• Article Type: journal article
• Data Source:
  • IRDB
  • NDL
  • CiNii Articles