Fine-grained power gating based on the controlling value of logic gates (VLSI設計技術) Fine-Grained Power Gating Based on the Controlling Value of Logic Gates

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Author(s)

Abstract

Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating approach based on the controlling value of logic gates is proposed for leakage power reduction. In the method, sleep signals of the power-gated blocks are extracted based on the probability of the controlling value of logic gates without any extra control logic. A basic algorithm and a probability-based heuristic algorithm have been developed to implement this method. The steady maximum delay constraint has also been introduced to handle the delay overhead. Experiments on the ISCAS'85 benchmarks show the effectiveness of our algorithms and the effect on the extra delay.

Journal

  • IEICE technical report

    IEICE technical report 108(23), 19-24, 2008-05-09

    The Institute of Electronics, Information and Communication Engineers

References:  11

Codes

  • NII Article ID (NAID)
    110006825164
  • NII NACSIS-CAT ID (NCID)
    AN10013323
  • Text Lang
    ENG
  • Article Type
    ART
  • ISSN
    09135685
  • NDL Article ID
    9526867
  • NDL Source Classification
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL Call No.
    Z16-940
  • Data Source
    CJP  NDL  NII-ELS 
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