書誌事項
- タイトル別名
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- Multi-bit Neuron MOS Comparator Realized with a Single Circuit
- タンイツ カイロ ニ ヨル ニューロン MOS コンパレータ ニ カンスル イチ コウサツ
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With the rapid development of the integrated circuit technology, the dynamic reconfigurable circuit has attracted much attention. The single circuit neuron MOS comparator has already been achieved. We propose the expansion of the circuit to achieve a multi-bit comparator. The proposed neuron MOS comparator is constructed by using only a two-stage neuron MOS inverter and an ordinary CMOS inverter. The newly designed circuit with an expanded Floating-Gate Potential Diagram (FPD) is described. The proposed circuit with three comparator functions is achieved using the single circuit. Applying this single circuit design technique, a multiple bits comparator can be achieved in a smaller area compared with that designed using the conventional circuit. The prototype of the newly proposed circuit was fabricated in the 1.2μm double poly-silicon CMOS process. The prototype device operates as well as the simulated one.
収録刊行物
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- 映像情報メディア学会誌
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映像情報メディア学会誌 60 (5), 807-812, 2006
一般社団法人 映像情報メディア学会
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詳細情報 詳細情報について
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- CRID
- 1390282680075343104
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- NII論文ID
- 110006838498
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- NII書誌ID
- AN10588970
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- ISSN
- 18816908
- 13426907
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- NDL書誌ID
- 7945157
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
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- 抄録ライセンスフラグ
- 使用不可