高性能と低消費電力を両立する可変パイプライン構造の再構成デバイスへの適用  [in Japanese] The Apprication of changeable pipeline steps archiecture to Reconfigurable devices  [in Japanese]

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Abstract

近年、モパイルコンピューティングからハイパフォーマンスコンピューティングに至るまで,幅広い分野において低消費エネルギーと高性能の両立が要求されおり,様々な手法が検討されている.著者らはその一手法として可変パイプライン段数アーキテクチャ (VSP) を提案している. VSP (Variable Stages Pipeline) はパイプライン段数を勤的に変化させ,同時にグリッチの緩和を行うことで,高性能と低消費電力の両立を実現できる.本稿では,この VSP の再構成デバイスへの適用を試みる。再構成デバイスは ASIC と比べ製造コスト的にも安価であり,最先端半導体プロセス技術によりトランジスタの集積度も向上しつつあるため,その使用範囲は拡大してきている. VSP の要素技術である LDS-Cell (Latch-DFF-Selector Cell) は,グリッチの緩和のためにその動作を D-FF または D-Latch として切り替えるが,低電力化のため特殊な構成になっており,再構成デバイスを用いて効率的に VSP をマッピングするのは困難である.そこで LDS-Cell を再構成デバイスに直接組み込むことにより VSP を適用可能にし,評価を行い再構成デバイスへの VSP の適用の有効性を示す.Recently, in the field of not only mobile computing but also high performance computing, the achivement of low energy computing and high performance computing is required, so various techniques are examined. We are proposing changeable pipeline steps architecture (VSP) as one of the methods. VSP (Variable Stages Pipeline) can dynamically change the number of pipeline steps and ease Glitch at the same time, and achieve high performance computing and low energy computing. In this paper, We propose the method of application of VSP to Reconfigurable devices. Reconfiguarable devices is inexpensive in the manufacturing cost compared with ASIC, and semiconductor technologies are advancing. LDS-Cell (Latch-DFF-Selector Cell) is a essensial tequnique of VSP, but it is difficult to mapping VSP at the Reconfigurable devices because of the paricular structure of LDS-Cell. We persent the Reconfigurable devices with LDS-Cell to find the effectiveness of VSP in Reconfigurable devices.

Recently, in the field of not only mobile computing but also high performance computing, the achivement of low energy computing and high performance computing is required, so various techniques are examined. Authors are proposing changeable pipeline steps architecture (VSP) as one of the methods. VSP (Variable Stages Pipeline) can dynamically change the number of pipeline steps and ease Glitch at the same time, and achieve high performance computing and low energy computing. In this paper, We propose the method of application of VSP to Reconfigurable devices. Reconfiguarable devices is inexpensive in the manufacturing cost compared with ASIC, and semiconductor technologies are advancing. LDS-Cell (Latch-DFF-Selector Cell) is a essensial tequnique of VSP, but it is difficult to mapping VSP at the Reconfigurable devices because of the paricular structure of LDS-Cell. We persent the Reconfigurable devices with LDS-Cell to find the effectiveness of VSP in Reconfigurable devices.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 2008(75(2008-ARC-179)), 43-48, 2008-07-29

    Information Processing Society of Japan (IPSJ)

References:  5

Codes

  • NII Article ID (NAID)
    110006946147
  • NII NACSIS-CAT ID (NCID)
    AN10096105
  • Text Lang
    JPN
  • Article Type
    Technical Report
  • ISSN
    09196072
  • NDL Article ID
    9639006
  • NDL Source Classification
    ZM13(科学技術--科学技術一般--データ処理・計算機)
  • NDL Call No.
    Z14-1121
  • Data Source
    CJP  NDL  NII-ELS  IPSJ 
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