Performance Evaluation of Finite-Difference Time-Domain (FDTD) Computation Accelerated by FPGA-based Custom Computing Machine

• SANO Kentaro

  Graduate School of Information Sciences, Tohoku University

• HATSUDA Yoshiaki

  Graduate School of Information Sciences, Tohoku University

• WANG Luzhou

  Graduate School of Information Sciences, Tohoku University

• YAMAMOTO Satoru

  Graduate School of Information Sciences, Tohoku University

抄録

This paper evaluates the performance of the 2D FDTD computation on our FPGA-based array processor. So far, we have proposed the systolic computational-memory architecture for custom computing machines tailored for numerical computations with difference schemes, and implemented the array-processor based on this architecture with a single ALTERA StratixII FPGA. The array processor is composed of a two-dimensional array of programmable PEs with mesh network so that computations on a grid are performed in parallel. We wrote and executed codes for the 2D FDTD computation on the array-processor. We obtained almost the same results by FPGA as those by AMD Athlon64 processor. In comparison with AMD Athlon64 processor running at 2.4 GHz, the array-processor operating at 106 MHz achieved over 7 times faster computation for the 2D FDTD problem, which corresponds to the actual performance of 16.2 GFlop/s. The high utilization of the adders and the multipliers of the array processor means that the architecture is also suitable for the FDTD method.

収録刊行物

• Interdisciplinary Information Sciences

  Interdisciplinary Information Sciences 15 (1), 67-78, 2009

  東北大学大学院情報科学研究科ジャーナル編集委員会

キーワード

• FDTD method
• Custom Computing Machine
• FPGA

詳細情報

• CRID: 1390282679412977280
• NII論文ID: 110007317981
• NII書誌ID: AA11032627
• DOI: 10.4036/iis.2009.67
• ISSN: 13476157
• ISSN: 13409050
• HANDLE: 10097/45569
• Web Site: https://tohoku.repo.nii.ac.jp/records/41759
• 本文言語コード: en
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