A Low Power Deterministic Test Using Scan Chain Disable Technique

• YOU, Zhiqiang

• IWAGAKI, Tsuyoshi

• INOUE, Michiko

• FUJIWARA, Hideo

抄録

This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.

identifier:https://dspace.jaist.ac.jp/dspace/handle/10119/4700

収録刊行物

• IEICE TRANSACTIONS on Information and Systems

  IEICE TRANSACTIONS on Information and Systems E89-D (6), 1931-1939, 2006-06-01

  電子情報通信学会

キーワード

• low power testing
• full scan testing
• deterministic test
• scan chain disable
• tabu search algorithm

詳細情報

• CRID: 1050282812513869056
• NII論文ID: 110007503110
• NII書誌ID: AA10826272
• ISSN: 09168532
• Web Site: http://hdl.handle.net/10119/4700
• 本文言語コード: en
• 資料種別: journal article
• データソース種別:
  • IRDB
  • CiNii Articles