Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology

• ITO Hiroyuki

  Integrated Research Institute, Tokyo Institute of Technology

• SUGITA Hideyuki

  Integrated Research Institute, Tokyo Institute of Technology

• OKADA Kenichi

  Integrated Research Institute, Tokyo Institute of Technology

• ITO Tatsuya

  Electron Device Laboratory, Fujikura Ltd.

• ITOI Kazuhisa

  Electron Device Laboratory, Fujikura Ltd.

• SATO Masakazu

  Electron Device Laboratory, Fujikura Ltd.

• YAMAUCHI Ryozo

  Fujikura Ltd.

• MASU Kazuya

  Integrated Research Institute, Tokyo Institute of Technology

Abstract

This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90° directional coupler using the WL-CSP technology has center frequency of 25.6GHz, insertion loss of -0.5dB and isolation of -29.8dB in the measurement result. The WL-CSP technology contributes to realize low-loss RF passive devices on Si CMOS chip, which is indispensable to achieve small-size, cost-effective and low-power monolithic wireless communication circuits (MWCCs).

Journal

• IEICE transactions on electronics

  IEICE transactions on electronics 90 (3), 641-643, 2007-03-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• wafer-level chip scale package
• RF CMOS
• passive device

Details

• CRID: 1572543027392636544
• NII Article ID: 110007519598
• NII Book ID: AA10826283
• ISSN: 09168524
• Text Lang: en
• Data Source:
  • CiNii Articles