Technology Mapping Technique for Increasing Throughput of Character Projection Lithography

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Abstract

The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.

Journal

  • IEICE Trans. Electronics, C

    IEICE Trans. Electronics, C 90(5), 1012-1020, 2007-05-01

    The Institute of Electronics, Information and Communication Engineers

References:  19

Cited by:  3

Codes

  • NII Article ID (NAID)
    110007519668
  • NII NACSIS-CAT ID (NCID)
    AA10826283
  • Text Lang
    ENG
  • Article Type
    Journal Article
  • ISSN
    09168524
  • Data Source
    CJP  CJPref  NII-ELS 
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