Design Methods of Radix Converters Using Arithmetic Decompositions

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Author(s)

    • SASAO Tsutomu
    • Department of Computer Science and Electronics, Kyushu Institute of Technology
    • MATSUURA Munehiro
    • Department of Computer Science and Electronics, Kyushu Institute of Technology

Abstract

In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. First, it considers Look-Up Table (LUT) cascade realizations. Then, it introduces a new design technique called arithmetic decomposition by using LUTs and adders. Finally, it compares the amount of hardware and performance of radix converters implemented by FPGAs. 12-digit ternary to binary converters on Cyclone II FPGAs designed by the proposed method are faster than ones by conventional methods.

Journal

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 90(6), 905-914, 2007-06-01

    The Institute of Electronics, Information and Communication Engineers

References:  13

Codes

  • NII Article ID (NAID)
    110007522146
  • NII NACSIS-CAT ID (NCID)
    AA10826272
  • Text Lang
    ENG
  • Article Type
    ART
  • ISSN
    09168532
  • Data Source
    CJP  NII-ELS 
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