A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses
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- YAMAUCHI Hiroyuki
- the Faculty of Information Engineering, Dept. of Computer Science and Engineering, Fukuoka Institute of Technology
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- SUZUKI Toshikazu
- the Corporate SLSI Development Div., Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
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- YAMAGAMI Yoshinobu
- the Corporate SLSI Development Div., Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
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抄録
A guarantee obligation of keeping a Static-Noise-Margin (SNM), a Write-Margin (WRTM), and a cell current (Icell) even against a simultaneous Read/Write (R/W) disturbed access at the same column is required for a 1R/1W (1R/1W) SRAM. We have verified that it is difficult for the previously proposed techniques so far to meet all the requirements simultaneously without any decrease in Icell or any significant area penalty. In order to address this issue, a new cell design technique for the 1R/1W SRAM cell with 8Tr's has been proposed and demonstrated in a 65nm CMOS technology. It has been shown that Icell in the R/W disturbed column can be increased by 77% and 195% at V_<dd>=0.9V and 0.6V, respectively, and a cell size can be reduced by 15%, compared with the conventional column-based cell power-terminal bias (VDDM) control assuming that the same Icell of 9μA at V_<dd>=0.9V has to be provided. Compared with the conventional scheme, it has been found that the proposed Write-Bit-Line precharge level (VWBL) control and column-based cell source-terminal bias (VSSM) control can provide a 1.45-times larger SNM for Write-Word-Line (WWL) disturbed cells and a 1.7-fold larger WRTM while keeping the same Icell, respectively.
収録刊行物
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- IEICE transactions on electronics
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IEICE transactions on electronics 90 (4), 749-757, 2007-04-01
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詳細情報 詳細情報について
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- CRID
- 1573950402323344000
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- NII論文ID
- 110007522174
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- NII書誌ID
- AA10826283
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- ISSN
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles