Design Method of High Performance and Low Power Functional Units Considering Delay Variations

  • WATANABE Kouichi
    Research Center for Advanced Science and Technology, the University of Tokyo
  • IMAI Masashi
    Research Center for Advanced Science and Technology, the University of Tokyo
  • KONDO Masaaki
    Research Center for Advanced Science and Technology, the University of Tokyo
  • NAKAMURA Hiroshi
    Research Center for Advanced Science and Technology, the University of Tokyo
  • NANYA Takashi
    Research Center for Advanced Science and Technology, the University of Tokyo

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Abstract

As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal transitions occur every cycle in all bits regardless of the input bit pattern. However, in functional units, a significant number of input bits may not change from the previous input in many cases. In such a situation, calculation of these bits is not required. Thus, we propose a method, called unflip-bits control, makes use of the above situation, to reduce energy consumption. We evaluate the energy consumption and performance penalty for the method using HSPICE and the verilog-XL simulator, and compare the method with the conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed asynchronous dual-rail circuit has a 12-60% lower energy consumption compared with a conventional asynchronous dual-rail circuit.

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Details 詳細情報について

  • CRID
    1571417127545052416
  • NII Article ID
    110007537855
  • NII Book ID
    AA10826239
  • ISSN
    09168508
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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