Manufacturability-Aware Design of Standard Cells
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- MUTA Hirokazu
- Department of Communications and Computer Engineering, Kyoto University
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- ONODERA Hidetoshi
- Department of Communications and Computer Engineering, Kyoto University
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Abstract
We focus our attention on the layout dependent Across Chip Linewidth Variability (ACLV) of gate-forming poly-silicon patterns as a measure for manufacturability, which is a major contributor of systematic gate-length variation. First, we study the ACLV of standard cell layouts by lithography simulation. Then, we introduce regularity in gate-forming poly-silicon patterns and how it improves the ACLV and also how it incurs area-overhead. According to the investigation, we propose two design guidelines for standard-cell layout that can reduce ACLV with reasonable area overhead. Those guidelines include on-grid fixed-pitch layout with dummy-poly insertion and stretched gate-poly extension. Design experiments assuming a 65nm process technology indicate that a D-FF designed with the first guideline reduces ACLV by 35% with 14% area overhead and the second guideline reduces ACLV by 75% with 29% area overhead at the best focus condition. Under defocus conditions, both layouts exhibit stable characteristics whereas the variability of conventional layout grows rapidly as the level of defocus increases. Circuit-level lithography simulation over benchmark circuits also supports that the proposed guidelines considerably reduces the amount of gate length variation.
Journal
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- IEICE Trans. on Electronics
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IEICE Trans. on Electronics 90 (12), 2682-2690, 2007-12-01
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1572261552475312384
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- NII Article ID
- 110007538012
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- NII Book ID
- AA10826239
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- ISSN
- 09168508
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- Text Lang
- en
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- Data Source
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- CiNii Articles