Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

• MOCHIZUKI Akira

  Research Institute of Electrical Communication, Tohoku University

• SHIRAHAMA Hirokatsu

  Research Institute of Electrical Communication, Tohoku University

• HANYU Takahiro

  Research Institute of Electrical Communication, Tohoku University

Abstract

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18μm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

Journal

• IEICE Trans. Electron., C

  IEICE Trans. Electron., C 89 (11), 1591-1597, 2006-11-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• differential-pair circuit
• current-mode circuit
• multiple-valued logic
• dynamic logic

Details

• CRID: 1570572702614569856
• NII Article ID: 110007538696
• NII Book ID: AA10826283
• ISSN: 09168524
• Text Lang: en
• Data Source:
  • CiNii Articles