Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing

• TAKAHASHI Tomohiro

  Research Institute of Electrical Communication, Tohoku University

• HANYU Takahiro

  Research Institute of Electrical Communication, Tohoku University

Abstract

This paper presents an asynchronous multiple-valued current-mode data-transfer controller chip based on a 1-phase dual-rail encoding technique. The proposed encoding technique enables "one-way delay" asynchronous data transfer because request and acknowledge signals can be transmitted simultaneously and valid states are detected by calculating the sum of dual-rail codewords. Since a key component, a current-to-voltage conversion circuit in a valid-state detector, is tuned so as to obtain a sufficient voltage range to improve switching speed of a comparator, signal detection can be performed quickly in spite of using 6-level signals. It is evaluated using HSPICE simulation with a 0.18-μm CMOS that the throughput of the proposed circuit based on the 1-phase dual-rail scheme attains 435Mbps/wire which is 2.9 times faster than that of a CMOS circuit based on a conventional 4-phase dual-rail scheme. The test chip is fabricated, and the asynchronous data-transfer behavior of the proposed scheme is confirmed.

Journal

• IEICE Trans. Electron, C

  IEICE Trans. Electron, C 89 (11), 1598-1604, 2006-11-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• network-on-chip (NoC)
• delay-insensitive
• dual-rail encoding
• globally asynchronous locally synchronous (GALS)
• point-to-point communication

Details

• CRID: 1571980077498134144
• NII Article ID: 110007538697
• NII Book ID: AA10826283
• ISSN: 09168524
• Text Lang: en
• Data Source:
  • CiNii Articles