A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

• NODA Hideyuki

  Renesas Technology Corp.

• DOSAKA Katsumi

  Renesas Technology Corp.

• MATTAUSCH Hans Jurgen

  Hiroshima University

• KOIDE Tetsushi

  Hiroshima University

• MORISHITA Fukashi

  Renesas Technology Corp.

• ARIMOTO Kazutami

  Renesas Technology Corp.

抄録

This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude compared with the conventional TCAM. We also propose a novel testing methodology of the soft-error rate with a fast parallel multi-bit test. In addition, the proposed architecture resolves the critical problem of the look-up table maintenance of TCAM. The design techniques reported in this paper are especially attractive for realizing soft-error immune, high-performance TCAM chips.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 89 (11), 1612-1619, 2006-11-01

  一般社団法人電子情報通信学会

キーワード

• soft error
• ECC
• TCAM
• embedded
• DRAM

詳細情報

• CRID: 1570009752661165056
• NII論文ID: 110007538699
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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