4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words

• JOHGUCHI Koh

  Research Center for Nanodevices and Systems, Hiroshima University

• MATTAUSCH Hans Jurgen

  Research Center for Nanodevices and Systems, Hiroshima University

• KOIDE Tetsushi

  Research Center for Nanodevices and Systems, Hiroshima University

• HIRONAKA Tetsuo

  Faculty of Computer Sciences, Hiroshima City University

抄録

The presented unified data/instruction cache design uses multiple banks and features 4 ports, distributed crossbar, different word-length for data and instruction ports, interleaved cache-line words and synchronous access with hidden precharge. A 20.5KByte storage capacity is integrated in 5-metal-layer CMOS logic technology with 200nm minimum gate length and a 3.4ns access-cycle time is achieved. The access bandwidth corresponds to 10 ports with standard word-length, while the cost in increased Si-area is only 25% in comparison to a 1-port cache.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 90 (11), 2157-2160, 2007-11-01

  一般社団法人電子情報通信学会

キーワード

• multi-port memory
• unified cache
• SRAM
• CMOS

詳細情報

• CRID: 1570854177591154560
• NII論文ID: 110007538855
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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