An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits

• UTAGAWA Akira

  Graduate School of Information Science and Technology, Hokkaido University

• ASAI Tetsuya

  Graduate School of Information Science and Technology, Hokkaido University

• HIROSE Tetsuya

  Graduate School of Information Science and Technology, Hokkaido University

• AMEMIYA Yoshihito

  Graduate School of Information Science and Technology, Hokkaido University

Abstract

We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulsedensity modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9dB compared with that of the uncoupled network as a result of noise shaping.

Journal

• IEICE Trans. Fundamentals, A

  IEICE Trans. Fundamentals, A 90 (10), 2108-2115, 2007-10-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• neuromorphic analog integrated circuits
• pulse density modulation
• noise shaping
• subthreshold CMOS circuits

Details

• CRID: 1571980077456881792
• NII Article ID: 110007540880
• NII Book ID: AA10826239
• ISSN: 09168508
• Text Lang: en
• Data Source:
  • CiNii Articles