CMOS Imaging Devices for New Markets of Vision Systems

• KAWAHITO Shoji

  Shizuoka University

抄録

This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 90 (10), 1858-1868, 2007-10-01

  一般社団法人電子情報通信学会

キーワード

• CMOS image sensor
• pinned photodiode
• noise reduction
• on-chip image processing
• A
• D conversion

詳細情報

• CRID: 1573105977363709056
• NII論文ID: 110007541172
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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