Hierarchical Predefined Codebook based Image Enlargement and Its FPGA Implementation

• TAMUKOH Hakaru

  Institute of Engineering, Tokyo University of Agriculture and Technology

• KAWANO Hideaki

  Faculty of Engineering, Kyushu Institute of Technology

• SUETAKE Noriaki

  Graduate School of Science and Engineering, Yamaguchi University

• SEKINE Masatoshi

  Institute of Engineering, Tokyo University of Agriculture and Technology

• CHA Byungki

  Faculty of Management and Information Sciences, Kyushu Institute of Information Sciences

• ASO Takashi

  Faculty of Management and Information Sciences, Kyushu Institute of Information Sciences

Bibliographic Information

Other Title

• 階層型事前定義コードブックに基づく画像拡大とそのFPGA実装(RFID関連技術,システムオンシリコン,一般)

Abstract

The codebook based method, which consists of a relationship of high- and low-frequency image components, achieves a high-quality image enlargement with high-frequency component augmentation. However, a codebook search process takes too much calculation time and it is not appropriate for a real-time application such as a moving image enlargement. To solve this problem, we propose a hierarchical predefined codebook to reduce the calculation cost and design a massively parallel and pipelined digital hardware architecture to realize the real-time codebook search. Simulation results show that the proposed method is 40 times faster than the ordinary method, and its FPGA implementation achieves a performance of around 54 fps for VGA size image enlargement.

Journal

• 電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム

  電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム 111 (342), 63-67, 2011-12-08

  The Institute of Electronics, Information and Communication Engineers

Keywords

• Image Enlargement
• Codebook
• FPGA

Details

• CRID: 1573105977704436736
• NII Article ID: 110009466382
• NII Book ID: AA1196239X
• Text Lang: ja
• Data Source:
  • CiNii Articles